1. Field of the Invention
Generally, the present invention relates to the field of fabricating microstructures such as integrated circuits, micromechanical structures and the like, and, more particularly, to the formation of structural elements by removing material in an etch tool.
2. Description of the Related Art
Presently, microstructures are integrated into a wide variety of products. One example in this respect is the employment of integrated circuits that, due to their relatively low cost and high performance, are increasingly used in many types of devices, thereby allowing superior control and operation of those devices. Due to economic reasons, manufacturers of microstructures, such as integrated circuits, are confronted with the task of steadily improving performance of these microstructures and/or reducing production costs with every new device generation appearing on the market. Manufacturing of microstructures is typically accomplished by producing a large number of substantially identical devices on a single substrate, wherein many manufacturing steps, such as depositing material layers and patterning material layers by etching, are performed simultaneously for all devices on the substrate. Thus, there is an ongoing drive in this field of industry to steadily increase the substrate size so as to place as many devices as possible on a single substrate, thereby increasing production yield.
On the other hand, an increasing substrate size may entail a plurality of issues in terms of substrate handling and process uniformity across the entire substrate area. The problem of process non-uniformities is even exacerbated as the critical dimensions of structural elements are reduced, since corresponding process tolerances, i.e., maximal allowable deviations from a design value, are also usually reduced, requiring an advanced process control.
One important process sequence in forming microstructures, such as sophisticated integrated circuits, is the transfer of a pattern provided in a mask layer into a material layer located underneath the mask layer by etching exposed portions of the lower material layer while substantially maintaining portions covered by the mask layer. Thus, a high degree of anisotropy in the material removal is necessary to obtain the required pattern with a minimum of under-etching. Etch processes of this type are configured as so-called dry etch processes performed in a gaseous atmosphere creating an anisotropic particle bombardment. In contrast, wet etch processes typically exhibit a substantially identical etch rate in all directions, i.e., an isotropic process, and therefore do not allow the formation of structural elements with lateral dimensions in a material layer having a thickness on the order of the lateral dimensions of the elements. The etch rate is herein defined as the thickness decrease of a specified material layer per time unit. For example, the etch rate may be expressed by nanometer per minute, or the like. Ideally, an etch process exhibits high selectivity to the material of the mask layer, frequently provided as a photoresist layer, and also to the material lying under the material to be removed. Moreover, a moderately high etch rate in the vertical direction and a negligible etch rate in the horizontal direction is preferred, unless a certain under-etching or an isotropic etching behavior is desired.
A large number of etch tools have been developed that more or less comply with the above-identified requirements. As the dimensions of the substrates are increasing, it becomes increasingly difficult to maintain process uniformity, i.e., a substantially constant etch rate, within the entire process chamber. In particular, it turns out that it is extremely difficult to establish substantially constant conditions over a distance of approximately some several hundred millimeters so that for substrate sizes of modern integrated circuits, i.e., 200 mm or even 300 mm, the etch tools are designed so as to process single substrates sequentially. Presently, a plurality of tool configurations are used to anisotropically or isotropically etch wafers. For instance, single wafer parallel plate reactors have a relatively simple configuration, in which the substrate is placed on one of two parallel electrodes so as to establish a plasma atmosphere over the substrate surface. Obtaining an appropriate etch rate uniformity across the entire substrate surface, however, requires an optimum gas distribution provided by a so-called shower head, which is difficult to achieve for substrates having a large diameter.
A further type of dry etching tool is a so-called magnetic-enhanced reactive ion etcher, in which the magnetron principle from sputter deposition tools is used to enhance the excitation process for primary electrons at lower gas pressures. Another type of etch tool is represented by downstream etchers, in which the reactive species are created in a plasma remote from the actual process chamber and are then transported to the process chamber. Since these etch tools lack the directionality of charged particles being directed to the substrate surface, the corresponding etch behavior is isotropical. Yet another tool configuration allowing good line width control, selectivity and low particle bombardment-induced damage is based on electrode-less, low pressure, high density plasma sources.
Despite the many successes achieved in the development of modern etch tools, it appears, nevertheless, that etch rate non-uniformities may occur in the range of several percent, depending on the specific etch tool and etch recipe used. In some applications, the etch rate non-uniformity may have a significant influence on the performance of the completed devices. For instance, modern integrated circuits formed in conformity with sophisticated CMOS technologies require extremely thin gate insulation layers to allow the fabrication of field effect transistors having a gate length in the deep sub-micron range. As a consequence, the patterning of an overlying gate electrode, typically provided as a doped polysilicon layer, necessitates a highly anisotropic accurate etch process that can be reliably stopped at the gate insulation layer without unduly damaging this layer. A non-uniformity of the etch rate may lead to a corresponding non-uniformity of the gate insulation layers, and, thus, of transistor performance of devices located at different areas of the substrate. A further example, in view of a minimal etch non-uniformity, is the formation of vias and trenches in a low-k dielectric, which is increasingly used in forming copper-based metallization layers.
In some approaches for forming these metallization layers, the vias are formed first and, subsequently, the trenches are etched without employing an etch stop layer so as to not unduly compromise the total permittivity of the low-k dielectric. Since the finally obtained depth of the trenches is merely controlled by the etch time, a corresponding non-uniformity of the etch rate may lead to a corresponding variation of the trench depth and may thus result in a significant conductivity variation after the trenches are filled with copper.
In view of the problems identified above, there exists a need for an improved technique that may provide increased etch rate uniformity in modern etch tools. The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.